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INTEGRATED CIRCUITS
DATA SHEET
TDA4887PS 160 MHz bus-controlled monitor video preamplifier
Product specification File under Integrated Circuits, IC02 2001 Oct 19
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Signal input stage Electronic potentiometer stages Output stage Pedestal blanking Output clamping and feedback references Clamping and blanking pulses On Screen Display insertion and OSD contrast Subcontrast adjustment, contrast modulation and beam current limiting I2C-bus control I2C-bus data buffer LIMITING VALUES THERMAL CHARACTERISTICS 10 11 12 12.1 12.2 12.3 12.4 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19 CHARACTERISTICS I2C-BUS PROTOCOL
TDA4887PS
TEST AND APPLICATION INFORMATION Test board Application board with monolithic post amplifier Building the application board Application hints INTERNAL CIRCUITRY PACKAGE OUTLINE SOLDERING Introduction to soldering through-hole mount packages Soldering by dipping or by solder wave Manual soldering Suitability of through-hole mount IC packages for dipping and wave soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2001 Oct 19
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
1 FEATURES
TDA4887PS
* 160 MHz pixel rate * 2.7 ns rise time, 3.6 ns fall time * I2C-bus control * I2C-bus data buffer for synchronization of adjustments * 8-bit Digital-to-Analog Converters (DACs) * 200 ns input clamping pulse * 4.6 V (p-p) output signal * Brightness control with grey scale tracking for user-friendly performance (4 dB more than TDA4885 and TDA4886) * Brightness control without grey scale tracking for easy alignment * On Screen Display (OSD) mixing with 50 MHz pixel rate * OSD contrast * Negative feedback for DC-coupled cathodes * Especially for AC-coupled cathodes - Bus controlled black level adaptable to post amplifier type - Internal positive feedback - DAC outputs for black level restoration * Integrated black level storage capacitors * Beam current limiting * Subcontrast/contrast modulation * Adjustable pedestal blanking * Sync clipping. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA4887PS SDIP24 DESCRIPTION plastic shrink dual in-line package; 24 leads (400 mil) VERSION SOT234-1 2 GENERAL DESCRIPTION The TDA4887PS is a monolithic integrated RGB preamplifier for colour monitor systems (e.g. 15" and 17") with I2C-bus control and OSD. In addition to bus control, beam current limiting and contrast modulation are possible. The IC offers brightness control with or without grey scale tracking for easy alignment. The signals are amplified to drive commonly used video modules or discrete solutions. A choice can be made between individual black level control with negative feedback from the cathode (DC coupling), or black level control with positive feedback and three DAC outputs for external cut-off control (AC coupling). The circuit can be used with special advantages in conjunction with the TDA485x monitor deflection IC family.
2001 Oct 19
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
4 QUICK REFERENCE DATA SYMBOL VP IP VP(n) IP(n) Vi(n)(b-w) Vo(n)(b-w)(max) PARAMETER supply voltage (pin 7) supply current (pin 7) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) supply current; channels 1, 2 and 3 (pins 21, 18 and 15) input voltage; channels 1, 2 and 3 (pins 6, 8 and 10) (black-to-white value) maximum output voltage swing (black-to-white value); channels 1, 2 and 3 (pins 22, 19 and 16) output voltage level (pins 22, 19 and 16) peak output source current (pins 22, 19 and 16) peak output sink current (pins 22, 19 and 16) black level reference voltage (pins 22, 19 and 16) DC coupling AC coupling tr(n) tf(n) Vo(n) ct(f) C Gtrack G Vbl(n) rise time of fast transients at signal outputs (pins 22, 19 and 16) fall time of fast transients at signal outputs (pins 22, 19 and 16) overshoot/undershoot at signal outputs (pins 22, 19 and 16) crosstalk suppression by frequency contrast control: colour signal related to maximum colour signal tracking of output colour signals of channels 1, 2 and 3 gain control related to maximum gain brightness control (difference between video black level and reference black level at signal outputs related to maximum colour signal) brightness control range (DAC output voltages for AC coupling or internal feedback reference voltage for DC coupling) control bit BRI = 0 contrast control from maximum to minimum input rise/fall times = 1 ns; maximum colour signal f = 50 MHz during fast positive signal transients during fast negative signal transients typical values control bit FPOL = 0 control bit FPOL = 1; no pedestal blanking 0.5 0.53 - - - 25 -45 - - - 2.7 3.6 - - - 0 CONDITIONS
TDA4887PS
MIN. TYP. 7.6 - 7.6 - - 8.0 25 8.0 20 0.7 4.6
MAX. 8.8 30 8.8 25 1.0 4.9
UNIT V mA V mA V V
maximum contrast; 4.2 maximum gain; Vi(n)(b-w) = 0.7 V; RL = 2 k 0.1 -40 -
Vo(n) Io(n)(source)(M) Io(n)(sink)(M) Vbl(n)(ref)
- - -
VP(n) - 1 - 20
V mA mA
2.0 1.89 - - 10 - 0 0.5 0 +33
V V ns ns % dB dB dB dB %
-13.5 - -10 -
VDA(n)
from maximum to minimum; control bit BRI = 1
-1.4
-
0
V
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
SYMBOL VFB/Rn PARAMETER DAC output voltage range without brightness control (for black level restoration) (pins 23, 20 and 17) maximum OSD colour signal related to maximum colour signal (pins 22, 19 and 16) OSD colour signal related to maximum OSD colour signal CONDITIONS control bit FPOL = 1; control bit BRI = 0 maximum OSD contrast; maximum gain OSD contrast control from maximum to minimum
TDA4887PS
MIN. TYP. 3.95 -
MAX. 5.75
UNIT V
VOSDn(max)
-
96
-
%
OC
-12
-
0
dB
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2001 Oct 19
LIM 24 VI1 6 VI2 8
5
Philips Semiconductors
160 MHz bus-controlled monitor video preamplifier
SDA SCL 12 4 REGISTER 8 DISO DISV FPOL BRI 4 8 8 13
BLOCK DIAGRAM
8
8
2
3
8
8
8
I2C-BUS
8-BIT DAC
4-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
2-BIT DAC
3-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
SUBCONTRAST CONTRAST MODULATION LIMITING
BRIGHTNESS SWITCH AC BLACK LEVEL
BRI
21
VP1
INPUT CLAMPING BLANKING
CONTRAST
GAIN 22 VO1
OSD CONTRAST
BRIGHTNESS PEDESTAL BLANKING CHANNEL 1 REFERENCE 23 18 FB/R1 VP2
FPOL INPUT CLAMPING BLANKING CONTRAST GAIN
FPOL
19 OSD CONTRAST BRIGHTNESS PEDESTAL BLANKING CHANNEL 2 REFERENCE 20 15 FPOL FPOL CONTRAST GAIN 16 OSD CONTRAST BRIGHTNESS PEDESTAL BLANKING BRIGHTNESS BLANKING CHANNEL 3 REFERENCE 17
VO2
6
VI3 10
FB/R2 VP3
INPUT CLAMPING BLANKING
VO3
fast blanking
TDA4887PS
FPOL blanking blanking output clamping DISV SUPPLY FPOL
FB/R3
input clamping DISO OSD INPUT
14
INPUT CLAMPING VERTICAL BLANKING 4 5 CLI
BLANKING OUTPUT CLAMPING 11 HFB
GNDX
TDA4887PS
Product specification
1
2
3
7 VP
9
MHB943
FBL OSD1 OSD2 OSD3
GND
Fig.1 Block diagram.
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
6 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION fast blanking input for OSD insertion OSD input, channel 1 OSD input, channel 2 OSD input, channel 3 input clamping and vertical blanking input signal input, channel 1 supply voltage signal input, channel 2 ground signal input, channel 3 output clamping and blanking input I2C-bus serial data input/output I2C-bus clock input ground signal, channels 1, 2 and 3 supply voltage, channel 3 signal output, channel 3 feedback input/reference voltage output channel 3 supply voltage, channel 2 signal output, channel 2 feedback input/reference voltage output, channel 2 supply voltage, channel 1 signal output, channel 1 feedback input/reference voltage output, channel 1 subcontrast adjustment, contrast modulation and beam current limiting input
TDA4887PS
SYMBOL FBL OSD1 OSD2 OSD3 CLI VI1 VP VI2 GND VI3 HFB SDA SCL GNDX VP3 VO3 FB/R3 VP2 VO2 FB/R2 VP1 VO1 FB/R1 LIM
handbook, halfpage
FBL 1 OSD1 2 OSD2 3 OSD3 4 CLI 5 VI1 6
24 LIM 23 FB/R1 22 VO1 21 VP1 20 FB/R2 19 VO2
TDA4887PS
VP 7 VI2 8 GND 9 VI3 10 HFB 11 SDA 12
MHB919
18 VP2 17 FB/R3 16 VO3 15 VP3 14 GNDX 13 SCL
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
7 FUNCTIONAL DESCRIPTION
TDA4887PS
The brightness setting is also valid for OSD signals. During blanking and output clamping the video black level will be blanked to the reference black level (brightness blanking). The brightness information is inserted before the gain potentiometers, background colour temperature will not change with brightness setting (grey scale tracking).
Refer also to block diagram (Fig.1) and definitions of levels and signals (Chapter 10). 7.1 Signal input stage
The RGB input signals are capacitively coupled into the TDA4887PS from a low-ohmic source (75 recommended) and actively clamped to the internal reference black level during signal black level. The signal amplitude is 0.7Vi(b-w) and should not exceed 1 V. The high-ohmic input impedance of the TDA4887PS allows the coupling capacitor to be relatively small (10 nF recommended). The coupling capacitor also functions as a storage capacitor between clamping pulses. Very small input currents will discharge the coupling capacitor resulting in black output signals for missing input clamping pulses. Composite signals will not disturb normal operation because a clipping circuit cuts all signal parts below black level. A fast signal blanking circuit included in the input stage is driven by several blanking pulses (see Section 7.6) and control bit DISV = 1. During the off condition the internal reference black level is inserted instead of the input signals. 7.2 7.2.1 Electronic potentiometer stages CONTRAST CONTROL
7.2.2.2
Brightness control without grey scale tracking
Brightness control without grey scale tracking is selected when control bit BRI = 1. The brightness information will be mixed with the DAC outputs for external black level restoration (FPOL = 1, AC-coupled cathodes) or internal feedback reference voltages (FPOL = 0, DC-coupled cathodes). This allows a simple bus-controlled brightness setting without grey scale tracking. With AC-coupled cathodes this is equivalent to brightness control via grid G1. 7.2.3 GAIN CONTROL AND GREY SCALE TRACKING
The gain control is driven by an 8-bit DAC via the I2C-bus. Gain control is used for white point adjustment (correction for different voltage-to-light amplification of the three colour channels) and therefore individually for R, G and B. The video signals related to the reference black level can be gain-controlled within a range of 14 dB (typical). This range is large enough to accommodate the maximum output amplitude for different applications. The nominal setting is maximum gain. The gain setting is also valid for OSD signals and brightness shift (BRI = 0), therefore the complete `grey scale' is effected by gain control. 7.3 Output stage
The contrast control is driven by an 8-bit DAC via the I2C-bus. The input signals related to the internal reference black level can be adjusted simultaneously by contrast control with a control range of 32 dB (typical). The nominal setting is for maximum contrast. 7.2.2 BRIGHTNESS CONTROL
7.2.2.1
Brightness control with grey scale tracking
The brightness control is driven by an 8-bit DAC via the I2C-bus; brightness control with grey scale tracking is selected when control bit BRI = 0. With brightness control, the video black level is shifted in relation to the reference black level simultaneously for all three channels. With a negative setting (up to 10% of the maximum signal amplitude) dark signal parts will be lost in ultra black; for positive settings (up to 33% of the maximum signal amplitude) the background will alter from black to grey. At nominal brightness setting (40H) there is no shift.
In the output stage the nominal input signal will be amplified to provide a 4.6 V (typical) output colour signal at maximum contrast and maximum gain settings. Reference or pedestal black levels are adjusted by output clamping. In order to achieve fast rise and fall times of the output signals with minimum crosstalk between the channels, each signal stage has its own supply voltage pin.
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
7.4 Pedestal blanking
TDA4887PS
For correct operation it is necessary that there is enough headroom for ultra black signals (negative brightness setting and pedestal blanking). Any clipping with the video supply voltage at the cathode can disturb the signal rise/fall times or the black level stabilization. After power-on, the control bit FPOL is set to logic 1 and all alignment registers are set to logic 0 resulting in the reference black level at its lowest level (0.53 V) with no output signal. Normal operation starts after all data registers have been refreshed via the I2C-bus. Brightness control with grey scale tracking (control bit BRI = 0) can be used as well as brightness control without grey scale tracking (control bit BRI = 1) using the mixing function of bus-controlled brightness offset (0 to -1.4 V) to feedback reference voltages (see Section 7.2). 2. AC-coupled cathodes (control bit FPOL = 1) For applications with AC-coupled cathodes the signal outputs are fed back internally. During the output clamping pulse they are compared with a bus controlled feedback reference voltage (0.5 to 1.9 V). These values ensure a good adaptability to both discrete and integrated post amplifiers. For black level restoration, the DAC outputs (FB/R1, FB/R2 and FB/R3) with a range of approximately 3.95 to 5.75 V can be used. Pedestal blanking is recommended because it allows use of a simple restoration circuit. After power-on, the DAC outputs will be at maximum output voltage (register value logic 0), so when using a non-inverting amplifier for the reference voltages the monitor will start with black. Brightness control with grey scale tracking (control bit BRI = 0) can be used as well as simple brightness control without grey scale tracking (control bit BRI = 1) using the mixing function of bus controlled brightness offset (0 to -1.4 V) to DAC output voltages (see Section 7.2).
The pedestal blanking is driven by a 2-bit DAC via the I2C-bus. Pedestal blanking inserts a negative output level related to the reference black level (should always correspond to the `extended cut-off voltage' at the cathode) during blanking and output clamping. In this way retrace lines during vertical flyback are suppressed (blanking to spot cut-off). The depth of pedestal blanking (voltage difference between reference black level and pedestal black level) is bus-controlled (2 bits, 0 to 13.5% of the maximum colour signal) and does not change with any other control or adjustment. The pedestal blanking level is used for output clamping instead of the reference black level (see Section 7.5). If the pedestal blanking level is the most negative output signal and if the application is for AC-coupled cathodes, a very simple black level restoration with a DC diode clamp can be used. 7.5 Output clamping and feedback references
The aim of the output clamping is to set the reference black level of the signal outputs to a value which corresponds to the `extended cut-off voltage' of the CRT cathodes. With missing output clamping pulses the integrated storage capacitors will be discharged resulting in output signals going to switch-off voltage. If using pedestal blanking, the pedestal black level will be controlled by output clamping (see Fig.5). It is therefore not allowed to change the pedestal depth after black level adjustment of the monitor. Feedback references are driven via the I2C-bus and controlled by an 8-bit DAC for DC feedback references or by a 3-bit DAC for AC feedback references: 1. DC-coupled cathodes (control bit FPOL = 0) The cathode voltage is divided by a voltage divider and fed back to the IC (pins FB/R1, FB/R2 and FB/R3). During the output clamping pulse it is compared with a bus-controlled feedback reference voltage with a range of approximately 5.75 to 3.95 V. Any difference will lead to a reference black level correction (subaddress 0BH = 00H) or pedestal black level correction (subaddress 0BH 00H) by charging or discharging the integrated capacitors that store the black level information between the output clamping pulses. The DC voltages of the output stages should be designed in such a way that the reference black level/pedestal black level is within the range of 0.5 to 2.4 V at the preamplifier output.
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
7.6 Clamping and blanking pulses 7.7
TDA4887PS
On Screen Display insertion and OSD contrast
There are two pins for clamping and blanking purposes (pins CLI and HFB): 1. Pin CLI (input clamping, vertical blanking) The pin CLI of TDA4887PS can be connected directly to pin CLBL of e.g. TDA4855 sync processor for input clamping pulses and vertical blanking pulses. Input clamping pulses and blanking pulses are completely separated from the sandcastle input, that means there is normally (outside detected vertical blanking) no blanking during input clamping and the clamping pulse is not suppressed during vertical blanking. The input pulse is scanned with two thresholds: a) 1.4 V (typical) for vertical blanking b) 3 V (typical) for input clamping. In order to separate the vertical blanking pulse from the sandcastle pulse it is necessary that the input clamping pulse has rise/fall times faster than 75 ns/V during the transition from 1.2 to 3.5 V and vice versa. The leading edge of the internal vertical blanking pulse is delayed by typically 270 ns (after the end of an input clamping pulse or the beginning of a separate blanking pulse), the trailing edge is delayed by typically 115 ns. During the vertical blanking pulse signal blanking, brightness blanking and pedestal blanking will be activated. In buffered mode, the leading edge of the internal vertical blanking pulse is used to synchronize data transmitted via the I2C-bus (see Section 7.10.1). For correct input clamping the input signals have to be at black level during the input clamping pulse. 2. Pin HFB (output clamping and blanking) The input pulse (e.g. horizontal flyback pulse) is scanned with two thresholds. If the input pulse exceeds the first threshold (typically 1.4 V) signal blanking, brightness blanking and pedestal blanking will be activated. If the input pulse exceeds the second threshold (typically 3 V) output clamping will be activated additionally. Especially for applications with DC-coupled cathodes (FPOL = 0), it is useful that the leading edge of the (internal) clamping pulse is slightly delayed with respect to the leading edge of the (internal) blanking pulse in order to avoid initial misclamping due to the delay of the feedback signal from the cathodes.
On Screen Display (OSD) insertion and OSD contrast are controlled by a 4-bit DAC driven via the I2C-bus. If the fast blanking input signal at pin FBL exceeds the threshold (typically 1.4 V) the input signals are blanked (signal blanking) and OSD signals are enabled. Then, any signal at pins OSD1, OSD2 or OSD3 exceeding the same threshold will create an insertion signal with an amplitude of 100% of the maximum colour signal. The amplitude can be controlled by OSD contrast (driven via the I2C-bus) with a range of 12 dB. The OSD signals are inserted at the same point as the contrast-controlled input signals and will be treated with brightness and gain control as with normal input signals. Identical pulses at OSD signal input pins and FBL have to be handled very carefully. Each difference in pulse delay at the inputs will produce glitches at pulse edges at signal outputs. When control bit DISO = 1 the OSD signal insertion and fast blanking (pin FBL) are disabled. 7.8 Subcontrast adjustment, contrast modulation and beam current limiting
The pin LIM is a linear contrast control pin which allows subcontrast setting, contrast modulation and beam current limiting. The maximum contrast is defined by the actual I2C-bus setting. Input signals at pin LIM act on video and OSD signals and do not affect the contrast bit resolution. If the pin is not used it should be decoupled with a capacitor or tied to the supply voltage. 7.8.1 BEAM CURRENT LIMITING
The open-circuit voltage is approximately 5 V, contrast reduction starts at input voltages <4.4 V (typical) and signal amplification will be reduced with descending input voltages. The input resistance of pin LIM is very high to make it possible to choose a time constant sufficient for the open-circuit voltage to recover through the application. 7.8.2 SUBCONTRAST
In order to fit the maximum signal amplification to the post amplifier gain, an input voltage of <4.4 V can be used. 7.8.3 CONTRAST MODULATION
To achieve brightness uniformity over the screen, scan dependent contrast modulation is possible. The nominal input voltage should be <4.4 V having enough margin for positive and negative modulation.
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
7.9 I2C-bus control 7.10 7.10.1 I2C-bus data buffer BUFFERED MODE
TDA4887PS
The TDA4887PS contains an I2C-bus receiver for several control functions: * Contrast register with control bits BRI, FPOL, DISV and DISO * Brightness control with 8-bit DAC * Contrast control with 8-bit DAC * OSD contrast control with 4-bit DAC * Gain control for each channel with 8-bit DAC * Internal feedback reference and external reference voltage control for each channel with 8-bit DAC * Black level for AC coupling with 3-bit DAC * Depth of pedestal blanking with 2-bit DAC. After power-up and after internal power-on reset of the I2C-bus, the registers are set to the following values (for most applications these settings guarantee a black screen after power-up): * Control bit FPOL set to logic 1 * Control bits BRI, DISV and DISO set to logic 0 * All other alignment registers set to logic 0 (minimum value for control registers). After an intermediate power dip, all registers are set to their initial values and an internal Power-on reset bit will be set with the consequence that the device will give no acknowledge on the data byte after being first addressed. The Power-on reset bit will be reset if the control register is addressed. It is recommended to then refresh all registers by using the auto-increment function.
Adjustments via the I2C-bus are synchronized with vertical blanking pulse at CLI: * Most significant bit (MSB) of subaddress is set to logic 1 * Only one I2C-bus transmission in buffered mode is accepted before the start of the vertical blanking pulse; following transmissions receive no acknowledge * Received data is stored in one internal 8-bit buffer * Adjustments will take effect with detection of the first vertical blanking pulse after the end of the acknowledged I2C-bus transmission * Waiting for vertical blanking pulse in buffered mode can be interrupted by Power-on reset * Auto-increment is not possible * Buffered mode should be used for user adjustments such as contrast, OSD contrast and brightness when a picture is visible on the monitor. 7.10.2 DIRECT MODE
Adjustments via the I2C-bus take effect immediately: * Most significant bit (MSB) of subaddress is set to logic 0 * Number of I2C-bus transmissions in direct mode is unlimited * Adjustments take effect directly at the end of each I2C-bus transmission * Direct mode can be used for all adjustments but large changes of control values may appear as visual disturbances in the picture on the monitor * Auto-increment is possible * Vertical blanking pulse is not necessary.
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VP VP(n) Vi(n) Vext PARAMETER supply voltage (pin 7) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) input voltage; channels 1, 2 and 3 (pins 6, 8 and 10) external DC voltage applied to pins 1 to 4 pins 5 and 11 pins 12 and 13 pins 23, 20 and 17 pins 22, 19 and 16 pin 24 Io(n)(av) Io(n)(M) Ptot Tstg Tamb Tj VESD average output current; channels 1, 2 and 3 (pins 22, 19 and 16) peak output current channels 1, 2 and 3 (pins 22, 19 and 16) total power dissipation storage temperature ambient temperature junction temperature electrostatic handling voltage for all pins machine model human body model Notes 1. No external voltages. 2. Equivalent to discharging a 200 pF capacitor via a 0.75 H inductance ("SNW-FQ-302B"). 3. Equivalent to discharging a 100 pF capacitor via a 1500 series resistor ("SNW-FQ-302A"). 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Rth(j-c) PARAMETER thermal resistance from junction to ambient thermal resistance from junction to case CONDITIONS in free air VALUE 55 5 note 2 note 3 -250 -3000 -0.1 -0.1 -0.1 -0.1 note 1 -0.1 - - - -25 -20 -25 CONDITIONS 0 0 -0.1 MIN.
TDA4887PS
MAX. 8.8 8.8 VP V V V
UNIT
VP VP + 0.7 VP VP + 0.7 note 1 VP 20 50 1400 +150 +70 +150 +250 +3000
V V V V V mA mA mW C C C V V
UNIT K/W K/W
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
10 CHARACTERISTICS All voltages and currents are measured in a dedicated test circuit (see Fig.17) optimized for best high frequency performance; all voltages are measured with respect to GND (pins 9 and 14); VP = VP1,2,3 = 8 V (pins 7, 21, 18 and 15); Tamb = 25 C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; maximum colour signals at signal outputs (pins 22, 19 and 16); reference black level (Vbl(ref)) approximately 0.7 V; nominal setting for brightness; maximum settings for OSD contrast, contrast and gain; no subcontrast, modulation of contrast or limiting (VLIM 5 V); no OSD fast blanking (pin 1 connected to ground); notes 1 to 3; unless otherwise specified. SYMBOL Supplies VP VP(SO) supply voltage (pin 7) supply voltage threshold at note 1 pin 7 at which signal outputs are switched off supply current (pin 7) supply voltage; channels 1, 2 and 3 (pins 21, 18 and 15) supply current; channels 1, pins 22, 19 and 16 2 and 3 (pins 21, 18 and 15) open-circuit; Vbl(n)(ref) = 0.7 V; notes 4 and 5 note 4 7.6 6.8 8.0 7.0 8.8 7.2 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IP VP(n) IP(n)
- 7.6 -
25 8.0 20
30 8.8 25
mA V mA
Input clamping and vertical blanking input, validation of buffered I2C-bus data (CLI; pin 5) VCLI input clamping and vertical blanking input signal notes 6 and 7 no vertical blanking, no input clamping vertical blanking, no input clamping input clamping, no vertical blanking ICLI input current VCLI = 1 V pin 5 connected to ground; note 8 VCLI = -0.1 V; note 8 tr/f5 rise/fall time for input clamping pulse; disable for vertical blanking width of input clamping pulse width of vertical blanking pulse for validation of buffered I2C-bus data delay between leading edge of vertical blanking pulse and validation of buffered I2C-bus data leading and trailing edge threshold VCLI = 1.4 V; note 7 I2C-bus buffered mode transmission completed; leading edge threshold VCLI = 1.4 V; note 7; see Fig.7 note 6; see Fig.7 -0.1 1.6 3.5 - -80 -250 - - - - -0.2 -45 -135 - +1.2 2.6 VP - -30 -100 75 V V V A A A ns/V
tW(CLI) tW(I2C)(valid)
200 10
- -
- -
ns s
td(I2C)(valid)
-
-
2
s
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
SYMBOL tdead(I2C) PARAMETER receiver dead time after synchronizing vertical blanking pulse following a completed I2C-bus buffered mode transmission delay between leading edges of vertical blanking input pulse and signal blanking at signal outputs I2C-bus CONDITIONS leading edge threshold VCLI = 1.4 V; note 7 15 MIN.
TDA4887PS
TYP. - -
MAX.
UNIT s
tdl5
VHFB < 0.8 V; input pulse rising and falling edges = 50 ns/V; threshold for vertical blanking with rising edge VCLI = 1.4 V; threshold for vertical blanking with falling edge VCLI = 3 V; see Fig.7 VHFB < 0.8 V; input pulse falling edge = 50 ns/V; threshold VCLI = 1.4 V; see Fig.7
-
270
-
ns
tdt5
delay between trailing edges of vertical blanking input pulse and signal blanking at signal outputs
-
115
-
ns
Output clamping and blanking input (HFB; pin 11) VHFB output clamping and blanking input signal note 9 no blanking, no output clamping blanking, no output clamping blanking, output clamping IHFB input current VHFB = 0.8 V pin 11 connected to ground; note 8 VHFB = -0.1 V; note 8 tW(HFB) width of output clamping pulse VHFB = 3 V -0.1 2 3.5 - -80 -250 1 - - - -0.4 -45 -135 - +0.8 2.6 VP - -30 -100 - V V V A A A s
Video signal inputs; channels 1, 2 and 3 (pins 6, 8 and 10) Vi(n)(b-w) Ii(n) input voltage; black-to-white value (pins 6, 8 and 10) DC input current (pins 6, 8 and 10) no input clamping; Vi(n) = Vi(n)(clamp); Tamb = -20 to +70 C during input clamping; Vi(n) = Vi(n)(clamp) 0.7 V Signal blanking ct(blank) crosstalk suppression from input to output during blanking control bit DISV = 1; f = 80 MHz control bit DISV = 1; f = 120 MHz 20 10 - - - - dB dB - 0.02 0.7 0.20 1.0 0.35 V A
350
420
500
A
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
SYMBOL Vclipp PARAMETER CONDITIONS - MIN.
TDA4887PS
TYP.
MAX.
UNIT
Clipping of negative input signals (measured at signal outputs) offset during sync clipping related to maximum colour signal Vi(n) = Vi(n)(clamp); sync amplitude = 0.3 V; note 10; see Fig.3 0.6 1.2 %
Contrast control; see Fig.8 and note 11 C Gtrack colour signal related to maximum colour signal tracking of output colour signals of channels 1, 2 and 3 FFH (maximum) 00H (minimum) FFH to 40H; note 12 - - - 0 -45 0 - - 0.5 dB dB dB
Fast blanking (pin 1) and OSD signal insertion; channels 1, 2 and 3 (pins 2, 3 and 4); note 13 VFBL fast blanking input signal (pin 1) no video signal blanking; OSD signal insertion disabled video signal blanking; OSD signal insertion enabled VOSDn OSD input signal (pins 2, 3 and 4) VFBL > 1.7 V no internal OSD signal insertion internal OSD signal insertion tr(OSDn) tf(OSDn) tg(n)(CO) rise time of OSD colour signals (pins 22, 19 and 16) fall time of OSD colour signals (pins 22, 19 and 16) width of (negative going) OSD signal insertion glitch, leading edge (pins 22, 19 and 16) width of (negative going) OSD signal insertion glitch, trailing edge (pins 22, 19 and 16) overshoot/undershoot of OSD colour signal related to actual OSD output pulse amplitude (pins 22, 19 and 16) 10 to 90% amplitude; pulse leading edge = 1.2 ns/V 90 to 10% amplitude; pulse falling edge = 1.2 ns/V identical pulses at fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4) identical pulses at fast blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4) pulse with 1.2 ns/V at OSD signal inputs (pins 2, 3 and 4) 0 1.7 - - 0 - - 3 4 4 1.1 VP 4 7 6 V V ns ns ns 0 - 1.1 V
1.7
-
VP
V
tg(n)(OC)
0
5
6
ns
VOSDn
-
6
10
%
VOSDn(max)
maximum OSD colour signal maximum OSD contrast; related to maximum colour maximum gain signal (pins 22, 19 and 16)
90
96
110
%
2001 Oct 19
15
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
SYMBOL OC PARAMETER CONDITIONS - -14 4.7 4.2 MIN.
TDA4887PS
TYP. -
MAX.
UNIT
OSD contrast control; see Fig.9 and note 14 OSD colour signal related to 0FH (maximum) maximum OSD colour signal 00H (minimum) 0 -12 5.0 4.4 dB dB -10 5.3 4.8
Subcontrast adjustment, contrast modulation and beam current limiting (pin 24); see Fig.8 and note 15 VLIM(nom) VLIM(start) nominal input voltage starting voltage for linear contrast and OSD contrast reduction stop voltage for linear contrast and OSD contrast reduction bandwidth of contrast modulation maximum input current -40 dB below maximum colour signal (contrast setting FFH) -3 dB VLIM = 0 V FFH (maximum); BRI = 0 40H (nominal); BRI = 0 00H (minimum); BRI = 0 pin 24 open-circuit V V
VLIM(stop)
1.5
2.0
2.5
V
BLIM ILIM(max) Vbl(n)
4 -1 28 -2 -12
- - 33 0 -10
- +1
MHz A % % %
Brightness control; see Figs 10, 12 and 14 and notes 16 and 17 difference between video black level and reference black level at signal outputs related to maximum colour signal DAC output voltage shift (pins 23, 20 and 17) 38 +2 -8
VDA(n)
FPOL = 1, see DAC output voltages for AC coupling or feedback reference voltage shift; FPOL = 0, see internal feedback reference voltage for DC coupling FFH (maximum); BRI = 1 00H (minimum); BRI = 1 - - - -15 -12 -8 -4 - -1.4 0 - - - -12.5 - - - - V V
Gain control; see Fig.11 and note 18 G video signal related to video signal at maximum gain FFH (maximum) 00H (minimum) 0 -13.5 -13.5 -9 -4.5 0 dB dB
Pedestal blanking; see Fig.5 and note 19 Vbl(n)(PED-VID) difference between pedestal black level and video black level at nominal brightness, measured at signal outputs (pins 22, 19 and 16) related to maximum colour signal 03H (maximum) 02H 01H 00H (minimum) % % % %
2001 Oct 19
16
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
SYMBOL PARAMETER CONDITIONS MIN.
TDA4887PS
TYP.
MAX.
UNIT
Signal outputs; channels 1, 2 and 3 (pins 22; 19 and 16) Vo(n)(min) Vo(n)(max) minimum output voltage level (pins 22, 19 and 16) maximum output voltage level (pins 22, 19 and 16) arbitrary input signals, contrast, brightness and gain adjustments; without load 0.01 VP(n) - 2 0.05 - 0.1 VP(n) - 1 V V
Io(n)(source)(max) Ro(n) Vo(n)(b-w)(max)
maximum output source current (pins 22, 19 and 16) output resistance (pins 22, 19 and 16) maximum output voltage maximum contrast; swing (black-to-white value); maximum gain; channels 1, 2 and 3 Vi(n)(b-w) = 0.7 V; RL = 2 k (pins 22, 19 and 16) peak output source current (pins 22, 19 and 16) peak output sink current (pins 22, 19 and 16) signal-to-noise ratio during fast positive signal transients during fast negative signal transients note 20
-15 65 4.2
- 75 4.6
- 90 4.9
mA V
Io(n)(source)(M) Io(n)(sink)(M) S/N
-40 - 48
- - -
- 20 -
mA mA dB
Frequency response at signal outputs; channels 1, 2 and 3 (pins 22, 19 and 16) tr(n) rise time of fast transients (pins 22, 19 and 16) input rise time = 1 ns; 10 to 90% amplitude; RL = 10 k; notes 21, 22 and 23; 2.8 V (p-p) signal amplitude; CL = 5 pF 4.5 V (p-p) signal amplitude; CL = 5 pF 4.5 V (p-p) signal amplitude; CL = 11 pF tf(n) fall time of fast transients (pins 22, 19 and 16) input fall time = 1 ns; 90 to 10% amplitude; RL = 10 k; notes 21, 22 and 23; 2.8 V (p-p) signal amplitude; CL = 5 pF 4.5 V (p-p) signal amplitude; CL = 5 pF 4.5 V (p-p) signal amplitude; CL = 11 pF - - - 3.6 3.6 5 4.5 4.5 6 ns ns ns - - - 2.7 3.2 3.8 3.8 4.2 4.5 ns ns ns
2001 Oct 19
17
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
SYMBOL Vo(n) PARAMETER overshoot of output signal pulse related to actual output pulse amplitude (pins 22, 19 and 16) undershoot of output signal pulse related to actual output pulse amplitude (pins 22, 19 and 16) ct(tr)(n) CONDITIONS input rise time = 1 ns; maximum colour signal - MIN.
TDA4887PS
TYP. -
MAX. 10
UNIT %
input fall time = 1 ns; maximum colour signal
-
-
10
%
Crosstalk at signal outputs; channels 1, 2 and 3 (pins 22, 19 and 16) transient crosstalk suppression (pins 22, 19 and 16) crosstalk suppression by frequency input rise/fall time = 1 ns; note 24 f = 50 MHz; note 25 f = 100 MHz; note 25 10 - - dB
ct(f)
25 10
- - 3.95 5.75 2.55 5.75
- - 4.1 5.9 2.7 5.9
dB dB
Internal feedback reference voltage for DC coupling; see Fig.12 and note 26 Vref(DC) internal reference voltage for FFH; FPOL = 0; BRI = 0 negative feedback polarity 00H; FPOL = 0; BRI = 0 (without brightness control) internal reference voltage for negative feedback polarity (with brightness control, see also brightness control VDA(n)) FFH; FPOL = 0; BRI = 1; maximum brightness 00H; FPOL = 0; BRI = 1; minimum brightness 3.7 5.6 2.3 5.6 V V V V
Output clamping, feedback inputs for DC coupling; FB/R1, FB/R2 and FB/R3 (pins 23, 20 and 17) IFB/Rn(max) maximum input current (pins 23, 20 and 17) minimum reference black level/minimum pedestal black level (pins 22, 19 and 16) maximum reference black level/maximum pedestal black level (pins 22, 19 and 16) black level variation at CRT black level decrease between clamping pulses related to maximum colour signal (pins 22, 19 and 16) during output clamping; -500 VHFB > 3.5 V; VFB/Rn = 0.5 V; FPOL = 0 VHFB > 3.5 V; FPOL = 0 0.01 -200 -60 nA
Vbl(n)(ref)(min)
0.1
0.5
V
Vbl(n)(ref)(max)
VHFB > 3.5 V; FPOL = 0
2.0
2.8
4.0
V
Vbl(CRT) Vbl(n)(lf)
FPOL = 0; note 27 FPOL = 0; fline = 60 kHz; = 10%
- -
- 0.1
200 -
mV %
2001 Oct 19
18
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
SYMBOL PARAMETER CONDITIONS MIN.
TDA4887PS
TYP.
MAX.
UNIT
Output clamping; internal feedback (of signal outputs) reference voltage for AC coupling; see Fig.13 and note 28 Vbl(n)(ref) reference black level voltage/pedestal black level voltage (pins 22, 19 and 16) VHFB > 3.5 V; FPOL = 1 00H (minimum) 0FH (maximum) 0.47 1.83 0.53 1.89 0.59 1.95 V V
DAC output voltages for AC coupling; FB/R1, FB/R2 and FB/R3 (pins 23, 20 and 17); see Fig.14 and note 29 VFB/Rn DAC output voltage (without brightness control) DAC output voltage (with brightness control, see also brightness control VDA(n)) RFB/Rn IFB/Rn(sink)(max) IFB/Rn(source)(max) output resistance maximum sink current maximum source current FFH; FPOL = 1; BRI = 0 00H; FPOL = 1; BRI = 0 FFH; FPOL = 1; BRI = 1; maximum brightness 00H; FPOL = 1; BRI = 1; minimum brightness FPOL = 1 FPOL = 1 FPOL = 1 3.7 5.6 2.3 5.6 - - - - 0 3 VIL = 0 V VIH = 5 V during acknowledge VOL = 0.4 V VOL = 0.6 V VSDA = 3 to 1.5 V; bus capacitance CSDA = 400 pF rising supply voltage falling supply voltage rising supply voltage falling supply voltage -10 -10 0 3 6 - - - - - 3.95 5.75 2.55 5.75 100 - -200 - - - - - - - - - 1.5 3.5 - 1.5 4.1 5.9 2.7 5.9 - 400 - V V V V A A
I2C-bus inputs; SDA (pin 12), SCL (pin 13); note 30 fSCL VIL VIH IIL IIH VOL ISDA(ack) to(f) Vth(POR)(r) Vth(POR)(f) SCL clock frequency LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level output voltage SDA output current (pin 12) during acknowledge output fall time threshold for Power-on reset on threshold for Power-on reset off 100 1.5 5 - - 0.4 - - 250 2.0 - 7 - kHz V V A A V mA mA ns V V V V
2001 Oct 19
19
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
Notes to the characteristics 1. Definition of levels (see Figs 3 to 5)
TDA4887PS
Reference black level: this is the level to which the input level is clamped during the input clamping pulse (VCLI > 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs: a) When the input is at black and the brightness setting is nominal (subaddress 01H = 40H) or control bit BRI = 1 b) During output blanking and clamping (VHFB > 3.5 V) if the pedestal blanking depth is set to zero (subaddress 0BH = 00H). Video black level: this is the black level of the actual video. At the input it is still equal to the reference black level. At the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level unaltered . Gain setting biases the video black level due to its influence on brightness. This is important for correct grey scale tracking. It can be observed at the outputs when the input is at black outside output blanking and clamping pulses (VHFB < 0.8 V). Pedestal black level: this is an ultra black level which deviates from the reference black level by a bus controlled amount. It can be observed at the output during output blanking and clamping (VHFB > 3.5 V; subaddress 0BH 00H). Switch-off voltage: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the internal black level storage capacitors if the supply voltage is less than VP(SO). It can be observed at the outputs when the input is at black, the brightness setting is nominal and VP < 6.8 V (subaddress 01H = 40H). Blanking level: this level equals reference black (subaddress 0BH 1= 00H) or pedestal black. It can be observed at the outputs during output blanking and clamping (VHFB > 3.5 V). 2. Explanation to black level adjustment: The three reference black levels are aligned correctly when they are made equal to the `extended cut-off levels' of the three cathodes. Full raster and spot cut-off can only be achieved by enabling the pedestal blanking or by applying a negative pulse to the grid G1. Negative feedback for DC-coupled cathodes (control bit FPOL = 0): the actual blanking level on the outputs depends on the external feedback application for output clamping. The loop will function correctly only if it is within the control range of Vbl(n)(ref)(min) to Vbl(n)(ref)(max) at pins 22, 19 and 16. It should be noted that changing pedestal blanking in a given application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black levels). Positive feedback for AC-coupled cathodes (control bit FPOL = 1): the feedback loop for output clamping is closed internally. The actual blanking level is bus controlled between 0.53 and 1.89 V (subaddress 0AH). It should be noted that changing pedestal blanking will not affect the blanking level, but instead shifts the video (and re-alignment of the three black levels is needed). 3. Definition of output signals (see Fig.6): Colour signal: all positive voltages are referenced to black level at signal outputs. Maximum colour signal: colour signal with nominal input signal 0.7Vi(b-w), maximum contrast setting and maximum gain setting. Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the superimposing of the brightness information (Vbl) and the colour signal. 4. The total supply current IP(tot) = IP + IP1 + IP2 + IP3 depends on the supply voltage with a factor of approximately 4.4 mA/V and varies in the temperature range from -20 to +70 C by approximately 5% (VO(n) = 0.7 V). 5. The channel supply current IP1, IP2, IP3 depends on the signal output current IO1, IO2, IO3, the channel supply voltage VP1, VP2, VP3 and the signal output voltage VO1, VO2, VO3. With IPx = IP(n) at IO(n) = 0, VP(n) = 8 V and VO(n) = 0.7 V: I P(n) I Px + I O(n) + 4.4 mA/V x ( V P(n) - 8 V ) - 1 mA/V x ( V O(n) - 0.7 V )
2001 Oct 19
20
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
6. Pin 5 should be used for input clamping and blanking during vertical retrace (signal blanking, brightness blanking and pedestal blanking). With a fast clamping pulse (transition between VCLI = 1.2 to 3.5 V and 3.5 to 1.2 V in less than 75 ns/V) no blanking will occur during input clamping. For 75 ns/V < tr/f5 280 ns/V the generation of the internal blanking pulse is uncertain. For tr/f5 > 280 ns/V the internal blanking pulse will be generated. If pin 5 is open-circuit, it will activate permanent input clamping and undefined blanking. 7. Pin 5 can be used to synchronize all adjustments via the I2C-bus (one by one). With a completed I2C-bus transmission in buffered mode, only the leading edge of a vertical blanking pulse activates an adjustment (see also Section 7.10). After the adjustment has been activated (validation of buffered I2C-bus data) the I2C-bus will be reset and further transmissions in direct or buffered mode are enabled. I2C-bus transmissions in direct mode need no synchronization pulses. 8. Input voltages less than -0.1 V can produce internal substrate currents which disturb the leakage currents at the signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or with negative voltage. Feeding clamping and blanking pulses via a resistor (several k) protects the pin from negative voltages. 9. Pin 11 should be used for output clamping and/or blanking. If pin 11 is open-circuit, it will activate permanent blanking and output clamping. 10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below input reference black level (see Fig.3). 11. Contrast control acts on internal colour signals under I2C-bus control; subaddress 02H (bit resolution 0.4% of contrast range). A 1 A 20 12. G track = 20 x maximum of log -------- x -------- A 10 A 2- A 1 A 30 log -------- x -------- A 10 A 3- A 2 A 30 log -------- x -------- dB A 20 A 3-
An: colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting. An0: colour signal output amplitude in channel n = 1, 2 or 3 at maximum contrast setting and same gain setting. 13. When OSD fast blanking is active and OSD inputs OSD1, OSD2 and OSD3 are HIGH (VFBL > 1.7 V, VOSD(n) > 1.7 V) the OSD colour signals will be inserted in front of the gain potentiometers. This ensures a correct grey scale of all video signals. The amplitudes of the inserted OSD signals can be controlled simultaneously by OSD contrast via the I2C-bus. The inserted black level change (Vbl) due to brightness control is not affected by OSD fast blanking. 14. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution 6.7% of OSD contrast range). 15. This pin can be used for subcontrast adjustment, beam current limiting and contrast modulation. Both the video and OSD contrast are reduced simultaneously (see Figs 8 and 9). Because of the high-ohmic input impedance the pin should be tied to a voltage of more than 5 V or decoupled with a capacitor (several nF) if not used. 16. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution 0.4% of brightness range). When control bit BRI = 1 the internal gain dependent brightness control is switched off and the feedback reference voltages (control bit FPOL = 0) or DAC output voltages for DC restoration (control bit FPOL = 1) at the cathodes are shifted with brightness control. 17. The voltage difference between video black level and reference black level is related to the colour signal (see note 3) with nominal 0.7 V (p-p) input signal, at maximum contrast (subaddress 02H = FFH) and for any gain setting. This voltage difference (in Volts) is proportional to the gain setting (grey scale tracking). Therefore Vbl (in percent) is constant for any gain setting. The given values of Vbl are valid only for video black levels higher than the minimum output voltage level Vo(n)(min).
2001 Oct 19
21
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
18. Gain control acts on video signals and inserted OSD video signals under I2C-bus control; subaddress 04H (channel 1), 05H (channel 2) and 06H (channel 3; bit resolution 0.4% of gain range respectively). 19. Pedestal blanking produces an ultra black level during blanking and output clamping which is the most negative signal at the signal output pins. The pedestal depth can be selected by bus control, subaddress 0BH. The reference black level which should correspond to the `extended cut-off voltage' at the cathodes is approximately Vbl(n)(PED-VID) higher (see Fig.5). The use of pedestal blanking with AC-coupled cathodes (control bit FPOL = 1) allows a very simple black level restoration with a DC diode clamp instead of a complicated pulse restoration circuit. 20. The signal-to-noise ratio is calculated using the formula (range 1 to 120 MHz): peak-to-peak value of the maximum signal output voltage S --- = 20 x log ------------------------------------------------------------------------------------------------------------------------------------------------------- dB RMS value of the noise output voltage N 21. The following formula can be used to approximately determine the output rise/fall time for any input rise/fall time other than 1 ns: t r/f, measured = t r/f (22,19,16) + ( t r/f, input - [ 1 ns ] ) 22. The relationship between pixel rate and signal bandwidth is f-3dB = 0.75 x fpixel, which is a compromise between excellent and acceptable video performance. The calculation of the pixel-related rise and fall times can be done using 0.35 0.35 the formula t r/f = ----------- = ---------------------------- . Although this formula is valid for low-pass filters of first order only it is used 0.75 x f pixel f -3dB 0.35 in most cases for simplified estimations. The pixel rate f pixel = -------------------- is a good approximation for many filter types. 0.75 x t r 23. Rise and fall times depend on signal amplitude, temperature, external load, black level and supply voltage. The rise time is affected if the top level of the signal pulse approaches the maximum output voltage level (high black level, large signal amplitude or low supply voltage). The fall time depends on the black level (increase with decreasing black level) and on large capacitive loads. Low-ohmic pull-down loads at the outputs helps towards smaller fall times. Rise and fall times increase with increasing ambient (or crystal) temperature. At maximum operating temperature, rise and fall times are approximately 0.4 ns longer than at Tamb = 25 C. 24. Transient crosstalk between any two output pins: a) Input conditions: any channel (channel A) with nominal input signal and 1 ns rise time. The inputs of the other two channels (channels B) are capacitively coupled to ground. Gain setting at maximum (FFH). Contrast setting at maximum (FFH). No limiting/modulation of contrast (VLIM 4.8 V) b) Output conditions: black level set to approximately 0.7 V for each channel at signal outputs. Output signals are VA and VB respectively VA c) Transient crosstalk suppression: ct(tr) = 20 x log ------ dB VB 25. Crosstalk by frequency between any two output pins: a) Input conditions: any channel (channel A) with 0.2 V (p-p) sinusoidal input signal, DC-coupled to approximately 4.3 V, no input clamping. The inputs of the other two channels (channels B) are capacitively coupled to ground. Gain setting at maximum (FFH). Contrast setting at maximum (FFH). No limiting/modulation of contrast (VLIM 4.8 V) b) Output conditions: control bit FPOL = 1, subaddress 0AH set to 01H, no pedestal blanking, nominal brightness setting. Output signals are VA and VB respectively VA c) Crosstalk suppression: ct(f) = 20 x log ------ dB VB
2 2 2 2
2001 Oct 19
22
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
26. Control bit FPOL = 0: the internal feedback reference voltages for DC control act under I2C-bus control; subaddress 07H (channel 1), 08H (channel 2) and 09H (channel 3); bit resolution 0.4% of voltage range. Rising values of the data bytes, e.g. 00H to FFH, correspond to rising values of the resulting reference black levels at signal outputs (pins 22, 19 and 16). The internal feedback reference voltages can be measured at feedback inputs (pins 23, 20 and 17) during output clamping (VHFB > 3.5 V) in closed feedback loop. The feedback loop remains operative at reference black levels between the specified values of Vo(n)bl(ref)(min) and Vo(n)bl(ref)(max). Control bit BRI = 1: the internal feedback reference voltages can be shifted under I2C-bus control which allows easy brightness control without grey scale tracking (see Section 7.2.2.2); subaddress 01H (bit resolution 0.4% of voltage shift range). The superimposition of internal feedback reference and brightness control leads to a voltage output range of 5.8 to 2.5 V. 27. Slow variations of video supply voltage VCRT will be suppressed at the CRT cathode by the clamping feedback loop. A change of VCRT with 5 V leads to a specified change of the cathode voltage. 28. To adapt to different types of post amplifier, the internal feedback reference voltage for AC coupling (control bit FPOL = 1) acts under I2C-bus control; subaddress 0AH (bit resolution 14.29%). The internal feedback reference voltage can be measured at signal outputs (pins 22, 19 and 16) during output clamping (VHFB > 3.5 V); reference black level or pedestal black level. 29. The DAC output voltages act under I2C-bus control for control bit FPOL = 1; subaddress 07H (FB/R1), 08H (FB/R2) and 09H (FB/R3); bit resolution 0.4% of voltage range respectively. Using an inverting amplifier for DC restoration, rising values of the data bytes, e.g. 00H to FFH, correspond to changing the light output from dark to bright. With control bit BRI = 1 the DAC output voltages can be shifted under I2C-bus control which allows easy brightness control without grey scale tracking (see Section 7.2.2.2); subaddress 01H (bit resolution 0.4% of voltage shift range). The superimposition of black level control and brightness control leads to a voltage output range of 5.8 to 2.5 V. 30. All adjustments via the I2C-bus can be synchronized with vertical blanking pulse at pin CLI. This is called I2C-bus transmission in buffered mode. Conversely the adjustments via the I2C-bus will take effect immediately in direct mode. The timing of I2C-bus transmissions in buffered mode is related to the vertical blanking. See Section 7.6 and note 7 for specification of vertical blanking input (pin 5).
2001 Oct 19
23
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
input video signal with sync pulses at pins 6, 8 and 10
input reference black level
the sync pulses are clipped to reference black level internally input clamping pulses at pin 5 output clamping and blanking input pulses at pin 11
MHA344
The input video signals have to be at black level during input clamping.
Fig.3 Definition of input signals.
2001 Oct 19
24
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth output clamping and
blanking input pulses at pin 11
signal outputs at pins 22, 19 and 16
(1)
maximum gain setting, maximum contrast setting, maximum/nominal/minimum brightness setting
(2)
(3)
video black levels at maximum brightness nominal brightness minimum brightness reference black level
switch-off voltage ground
(1)
maximum gain setting, maximum brightness setting, maximum/minimum contrast setting
(3)
video black level (maximum brightness) reference black level
switch-off voltage ground
maximum brightness setting, maximum contrast setting, maximum/minimum gain setting
(1)
(3)
video black levels (maximum brightness) reference black level
MHB920
switch-off voltage ground
(1) Maximum. (2) Nominal. (3) Minimum.
Fig.4 Definition of levels and functions of brightness, contrast and gain with no pedestal blanking.
2001 Oct 19
25
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth clamping and output
blanking input pulses at pin 11
signal outputs at pins 22, 19 and 16
no pedestal blanking maximum gain setting, maximum contrast setting, maximum/minimum brightness setting
(1)
(2)
video black levels at maximum brightness minimum brightness reference black level
switch-off voltage ground
pedestal blanking maximum gain setting, maximum contrast setting, maximum/minimum brightness setting
(1)
(2)
video black levels at maximum brightness minimum brightness reference black level
switch-off voltage ground
pedestal black level
MHB921
(1) Maximum. (2) Minimum.
Fig.5 Output signals with and without pedestal blanking.
2001 Oct 19
26
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
colour signals
video signals
(1) (2)
video black levels at maximum brightness minimum brightness
reference black level
MHB922
(1) Maximum brightness setting. (2) Minimum brightness setting.
Fig.6
Definition of output signals at pins 22, 19 and 16: maximum gain setting, maximum contrast setting and no pedestal blanking.
handbook, full pagewidth
3V input pulses at pin 5 t r/f5 75 ns/V 1.4 V
internal pulse for input clamping vertical blanking pulses at signal outputs (brightness blanking at maximum brightness setting) t dl5 t dl5 t dl5
video black level reference black level
MHB944
Fig.7 Timing of pulses at pin 5 and derived pulses at maximum brightness setting.
2001 Oct 19
27
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
MHB945
0
colour signal amplitude with respect to maximum colour signal amplitude -3 (dB)
(1)
contrast modulation range -6
(2)
- 12
- 45 00H 20H 40H 60H 80H A0H
(3)
C0H
E0H
FFH
contrast control data byte (1) No contrast reduction. (2) Partial contrast reduction by subcontrast, limiting or contrast modulation. (3) Full contrast reduction by subcontrast, limiting or contrast modulation.
Fig.8 Contrast control characteristic with subcontrast, limiting or contrast modulation.
handbook, full pagewidth
MHB946
maximum OSD signal amplitude 96 OSD signal amplitude with respect to maximum colour signal amplitude (%) maximum colour signal amplitude
(1)
(2)
24
(3)
00H OSD contrast control data byte (1) No OSD contrast reduction. (2) Partial OSD contrast reduction by subcontrast, limiting or contrast modulation. (3) Full OSD contrast reduction by subcontrast, limiting or contrast modulation.
0FH
Fig.9 OSD contrast control characteristic with subcontrast, limiting or contrast modulation.
2001 Oct 19
28
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
MHB947
33
difference of video black level and reference black level with respect to maximum colour signal amplitude (%) 0
(1)
(2)
-10
00H
20H
40H
60H
80H
A0H
C0H
E0H
FFH
brightness control data byte (1) Nominal adjustment. (2) Nominal brightness reference black level.
Fig.10 Brightness control characteristic; control bit BRI = 0.
handbook, full pagewidth
100 video signal gain with respect to maximum video signal gain (%)
MHB948
20
00H
20H
40H
60H
80H
A0H
E0H FFH C0H gain control data byte
Fig.11 Gain control characteristic.
2001 Oct 19
29
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
MHB949
5.75 internal feedback reference voltage (V) 4.35 3.95
(1)
(2)
brightness control; 8-bit DAC subaddress 01H
2.55
0 00H
20H
40H
60H
80H
A0H
C0H
E0H
FFH
negative feedback reference data byte
(1) Control bit BRI = 0 or control bit BRI = 1 and minimum brightness setting (subaddress 01H at 00H). (2) Control bit BRI = 1 and maximum brightness setting (subaddress 01H at FFH).
Fig.12 Internal feedback reference voltages for negative feedback (FPOL = 0).
handbook, full pagewidth
1.89 internal feedback reference voltage 1.70 (V) 1.50 1.31 1.11 0.92 0.72 0.53 0 01H 02H 03H 04H 05H 06H 07H
MHB950
positive feedback reference data byte
Fig.13 Internal feedback reference voltages for positive feedback (FPOL = 1).
2001 Oct 19
30
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
MHB951
5.75 DAC output voltage pins 23, 20, 17 (V) 4.35 3.95
(2) (1)
brightness control; 8-bit DAC subaddress 01H
2.55
0 00H
20H
40H
60H
80H
A0H
C0H
E0H
FFH
feedback reference data byte; subaddresses 07H, 08H and 09H
(1) Control bit BRI = 0 or control bit BRI = 1 and minimum brightness setting (subaddress 01H at 00H). (2) Control bit BRI = 1 and maximum brightness setting (subaddress 01H at FFH).
Fig.14 DAC output voltages (control bit FPOL = 1).
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31
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
11 I2C-BUS PROTOCOL Table 1 Slave address A5(1) 0 A4(1) 0 A3(1) 0 A2(1) 1 A1(1) 0
TDA4887PS
A6(1) 1 Notes 1. Address bit. 2. Write bit. Table 2 S(1) Notes
A0(1) 0
W(2) 0
Slave receiver format SLAVE ADDRESS A(2) SUBADDRESS(3) A DATA BYTE(4) A P(5)
1. START condition. 2. A = acknowledge. After an intermediate power dip all registers are set to their initial values (see note 3 at Table 4) and an internal power-on reset bit will be set with the consequence that the device will give no acknowledge on the data byte after a first addressing. The power-on reset bit will be reset if the control register is addressed. It is recommended to then refresh all registers by using the auto-increment function. 3. All subaddresses within the range 00H to 0BH are automatically incremented. The subaddress counter wraps around from 0BH to 00H. For subaddresses within the range 80H to 8FH no auto-increment takes place. Subaddresses outside the ranges 00H to 0BH and 80H to 8BH are acknowledged by the device but no auto-increment or any other internal operation takes place. 4. Single data byte in case of no auto-increment of subaddresses. More than one data byte with auto-increment of subaddresses. 5. STOP condition.
2001 Oct 19
32
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
Table 3 Subaddress byte format SUBADDRESS(1) FUNCTION Control register Brightness control Contrast control OSD contrast control Gain control channel 1 Gain control channel 2 Gain control channel 3 Black level reference channel 1 Black level reference channel 2 Black level reference channel 3 Black level for AC coupling Depth of pedestal blanking DIRECT MODE 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH
TDA4887PS
SUBADDRESS BYTE
BUFFERED S7(2) S6(2) S5(2) S4(2) S3(2) S2(2) S1(2) S0(2) MODE 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH B(3) B(3) B(3) B(3) B(3) B(3) B(3) B(3) B(3) B(3) B(3) B(3) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1
0CH to 0FH 8CH to 8FH Notes
not used
1. The most significant bit (MSB) of the subaddress enables an I2C-bus transmission in direct or in buffered mode (see note 3). Subaddresses outside the ranges 00H to 0FH and 80H to 8FH are not used. 2. Subaddress bit. 3. Most significant bit of subaddress byte. I2C-bus transmission in direct mode: B = 0. I2C-bus transmission in buffered mode: B = 1.
2001 Oct 19
33
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
Table 4 Subaddress and data byte format SUBADDRESS(1) FUNCTION Control register Brightness control Contrast control OSD contrast control Gain control channel 1 Gain control channel 2 Gain control channel 3 Black level reference channel 1 Black level reference channel 2 Black level reference channel 3 Black level for AC coupling Depth of pedestal blanking Notes 1. See Table 3 (Subaddress byte format). 2. The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0). DIRECT BUFFERED D7(4) D6(4) D5(4) MODE MODE 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH X(5) A17 A27 X(5) A47 A57 A67 A77 A87 A97 X(5) X(5) BRI A16 A26 X(5) A46 A56 A66 A76 A86 A96 X(5) X(5) X(5) A15 A25 X(5) A45 A55 A65 A75 A85 A95 X(5) X(5) DATA BYTE(2) D4(4) X(5) A14 A24 X(5) A44 A54 A64 A74 A84 A94 X(5) X(5) D3(4) D2(4) D1(4)
TDA4887PS
D0(4) X(5) A10 A20 A30 A40 A50 A60 A70 A80 A90 AA0 AB0
NOMINAL VALUE(3) 08H 40H FFH 0FH FFH FFH FFH - - - - 00
FPOL DISV DISO A13 A23 A33 A43 A53 A63 A73 A83 A93 X(5) X(5) A12 A22 A32 A42 A52 A62 A72 A82 A92 AA2 X(5) A11 A21 A31 A41 A51 A61 A71 A81 A91 AA1 AB1
3. Under certain conditions the nominal values lead to nominal colour signals, etc. (see notes 1 and 3 of Chapter "Characteristics" and Figs 4 to 6). After power-up and after internal Power-on reset of the I2C-bus the registers are set to the following values: a) Control bit FPOL to logic 1. b) Control bits DISV, DISO and BRI to logic 0. c) All other alignment registers to logic 0 (minimum value for control registers). 4. Data bit. 5. X means don't care but the bits are preferably set to logic 0 for software compatibility with other video ICs that have the same slave address.
2001 Oct 19
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
Table 5 BIT DISO = 0 DISO = 1 DISV = 0 DISV = 1 FPOL = 0 FPOL = 1 BRI = 0 BRI = 1 OSD signals enabled OSD signals disabled video signals enabled video signals disabled Control register FUNCTION
TDA4887PS
negative feedback polarity; pins 23, 20 and 17 as feedback inputs; no external DAC voltage outputs positive feedback polarity; pins 23, 20 and 17 as external DAC voltage outputs; internal feedback of signal outputs internal brightness control with grey scale tracking Brightness control without grey scale tracking. With FPOL = 0 the brightness information is combined with the internal feedback reference voltages. With FPOL = 1 the brightness information is combined with the DAC output voltages for DC restoration at the cathodes.
2001 Oct 19
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Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
START
LOAD PRESET CONTROL BITS FPOL, BRI DISV = 1 DISO = 1 load from program ROM code or EEPROM
LOAD FACTORY SETTINGS GAIN (CHANNEL 1, 2, 3) BLACK LEVEL REFERENCES (CHANNEL 1, 2, 3) OR EXTERNAL DAC VOLTAGES AC BLACK LEVEL PEDESTAL DEPTH
load from EEPROM
LOAD USER PRESET VALUES CONTRAST BRIGHTNESS OSD CONTRAST load from EEPROM
DEFLECTION CONTROL IC LOCKED yes DISV = 0 DISO = 0 DISPLAY NEW MODE(1) DISO = 1
no
USER INPUT
no
yes DISO = 0 RESPONSE TO USER INPUTS(2) (CONTRAST, BRIGHTNESS, OSD CONTRAST) DISO = 1
DEFLECTION CONTROL IC LOCKED
no DISV = 1
(1) Only synchronized video should be displayed. Each new mode can be displayed by OSD. (2) Data transmission should be synchronized with vertical blanking of the monitor.
yes
MHB932
Fig.15 I2C-bus control flow chart.
2001 Oct 19
36
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
12 TEST AND APPLICATION INFORMATION
handbook, full pagewidth
TDA4887PS
contrast modulation input
limiting input
subcontrast setting fast blanking 1 24 Application with integrated post amplifier, DC-coupled cathode and negative feedback. to cathode 90 V 4 signal inputs channel 1 6 19 21 BLACK LEVEL RESTORATION to cathode Application with integrated post amplifier, AC-coupled cathode and black level restoration cicuit.
2 OSD inputs
23
3
22
5
20
TDA4887PS
7 channel 2 8 17 18
70 V
9 channel 3 10
16
90 V
15
11
14
Application with discrete post amplifier, DC-coupled cathode and negative feedback. to cathode
12
13
8V
pull-up resistors I2C-BUS
5V
MHB933
output clamping blanking input clamping vertical blanking
Fig.16 Basic applications for different kinds of post amplifiers with DC or AC coupling.
12.1
Test board
For high frequency measurements, a special test board with only a few external components can be built. It utilizes the internal positive feedback of the output signals during output clamping with control bit FPOL = 1. Figure 17 2001 Oct 19 37
shows the test circuit and Figs 18 and 19 show the layout and mounting of the double-sided printed-circuit board. Most components are SMD-type. Short HF loops and minimum crosstalk between channels and between signal inputs and outputs are achieved by using properly shaped ground areas.
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
1 k
5.6 FBL FBL 50 OSD1 50 OSD2 50 OSD3 50 CLI 50 10 nF VI1 50 150 pF 5 k J1 10 nF VI2 50 150 pF 5 k J2 10 nF VI3 50 150 pF 5 k J3 HFB 50 150 pF 10 nF SDA 12 13 SCL HFB 11 14 GNDX VI3 10 15 VP3 150 pF 100 nF 5.6 0.47 F (63 V) GND 9 16 VO3 3.3 pF 10 k 0.47 F (63 V) 100 nF 100 pF VI2 8 17 FB/R3 channel 3 VO3 VP 7 VI1 6 19 VO2 3.3 pF VP2 150 pF 100 nF 5.6 0.47 F (63 V) FB/R3 solder pin 10 k 1 24 LIM
OSD1
2
23
FB/R1 channel 1
FB/R1 solder pin
OSD2
3
22
VO1 1 k VP1 150 pF 100 nF 5.6 0.47 F (63 V) FB/R2 3.3 pF 10 k
VO1
OSD3
4
21
CLI
5
20
FB/R2
solder pin channel 2 VO2
TDA4887PS
18
10 nF LIMAC 50 10 k SDA 5V SCL 10 k 10 nF 10 k
VPX VP1 sense VP sense VP GND VINDC LIM 5V
MHB934
Fig.17 Test board utilizing internal positive feedback only (FPOL = 1).
2001 Oct 19
38
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
103
81
CLI
OSD3
50 50
OSD2
50
OSD1
50
FBL
10 k
5.6 1 k
50
50 3.3 pF
VO1
150 pF 0.47 F 5.6
VI1
10 nF
10 nF 150 pF 5 k
100 nF
- +
1 k
U19
10 k 3.3 pF
VI2 50 VI3
J1 J2
0.47 F
VO2
TDA4887PS
100 nF 150 pF 10 k
150 pF 5 k 50 10 nF 5 k
+
- 0.47 F + - +
5.6
-
150 pF
J3
3.3 pF 100 nF 50 10 nF 150 pF 10 k 10 nF
VO3
0.47 F 5.6
HFB
50
10 k
10 k
SDA
SCL LIMAC
MHB935
Dimensions are in mm.
Fig.18 Printed-circuit top view shown with and without components mounted (for bottom view, see Fig.19).
2001 Oct 19
39
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
103
81
100 pF 100 nF
100 nF 100 pF
MHB217
Dimensions are in mm.
Fig.19 Printed-circuit bottom view shown with and without components mounted (for top view, see Fig.18).
2001 Oct 19
40
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
12.2 Application board with monolithic post amplifier
TDA4887PS
80 V supply and use of I2C-bus controlled external brightness setting. The 8 V supply voltage of the preamplifier is made from 12 V on this board. Connectors for video, sync, I2C-bus, OSD, clamping pulses, beam current limiting and supply voltages are provided.
Figure 20 shows the application circuit of TDA4887PS with a modern monolithic video post amplifier and AC-coupled CRT. The black level restoration circuit is designed for
2001 Oct 19
41
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
Vg2 1 2 3 4 5 6 7 8 9 10 11 12 R4 13 14 R5 1 k 1 4 3 2 1 8V R9 100 SDA 4 3 2 1 R7 10 k R8 9 10 k 10 15 C302 100 nF 16 D1 5.1 V C1 100 nF 7 C7 22 nF 8 17 R306 10 R304 5.6 N M R6 1 k R302 1 k R202 1 k R102 1 k 3 22 24 1 k R14 2.2 R12 100 C9 22 nF C2 330 nF 7808 C3 100 nF C6 100 F 8V G F R3 5.6 R2 1 R15/H 2.7 k R1 1 R16/H D 2.7 k E A L1 10 H L2 10 H B C12 1.5 nF C
BEAM CUR LIM V2 80 V V1 12 V CLAMPING BLANKING Vff Vff GND Vg1 GROUND HOR SYNC VERT SYNC AQUADAG n.c. n.c.
CH 1 CH 2 OSD CH 3 FBL
2
23 R106 10 R104 C102 100 nF 5.6
H
I
4
21
5
20 R206
J
6
19
I 2C-BUS
+5 V GND SCL
TDA4887PS
18
10 R204 C202 100 nF 5.6
K
L
VERT SYNC R10 HOR SYNC 100 R11 100 C101 CH 1 R101 75 22 nF R103 33
11
14
12
13
VIDEO INPUT
C201 CH 2 R201 75 22 nF
R203 33
C301 CH 3 R301 75 22 nF
R303 33
MHB966
Fig.20 Application board with LM2435 (drawing is continued in Fig. 20).
2001 Oct 19
42
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
TDA4887PS
handbook, full pagewidth
A B C EHT
D E C5 1 nF (2 kV) F R318/H 68 R13 G 4.7 C15 100 nF R107 22 L108 0.22 H D109 BAV103 D110 BAV103 R218/H 68 R118/H 68 10 9 571 C11 1 nF (2 kV) C10 1.5 nF
6 8 11
C106 1 F (63 V)
R119 1 M
Vfoc
C8 47 F
C4 H 47 F C14 I 2 x 100 nF 4 5 6 J 7 8 K 9 LM2435
1 R207 2 3 22 L208 0.22 H
D209 BAV103 D210 BAV103
C206 1 F (63 V)
R219 1 M
R307 22
L308 0.22 H
D309 BAV103 D310 BAV103
C306 1 F (63 V)
R319 1 M
D303 BAW62
R317 10 k
8V L R305 M 10 C304 2.2 nF N 8V TR201 R216 68 k R215 150 k C205 1 F (100 V) R214 12 k D103 BAW62 TR301 2x BC546 R316 68 k R315 150 k C305 1 F (100 V) R314 12 k D203 BAW62
TR302 R313 270
R217 10 k
R205 10
2x BC546
TR202 R213 270
C204 2.2 nF
R117 10 k
8V TR101 R116 68 k R115 150 k C105 1 F (100 V) R114 12 k
MHB967
R105 10
2x BC546
TR102 R113 270
C104 2.2 nF
Fig.21 Application board with LM2435 (drawing continued from Fig. 20).
2001 Oct 19
43
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
12.3 12.3.1 Building the application board GENERAL
TDA4887PS
12.4.1.2 Difficulty during monitor production
* Double-sided board * Short HF loops by large ground plane on the rear * SMD components with minimum parasitics. 12.3.2 VOLTAGE OUTPUTS
* Capacitive loads as small as possible * Be aware of internal output resistance (typically 75 ). 12.3.3 SUPPLY VOLTAGES
The factory cut-off alignment is done at a quite high level (e.g. 2.4 cd/m2). As a consequence it is not certain that the reference black level will match the cut-off exactly after a first black level adjustment. If then the R, G, B gains are adjusted for the (x, y) white point at e.g. 102.8 cd/m2, the white balance at 2.4 cd/m2 will have changed. So two or more alignment cycles may be needed to achieve good results.
12.4.1.3
Considerations for a single-pass factory alignment
* Capacitors as near as possible to the pins * Use electrolytic capacitors with small serial resistance and inductance. 12.3.4 FLASHOVER
The nominal brightness setting is 40H. In this condition the black level equals reference black level and must match to the CRT cut-off. For a better understanding, discrete values for luminance, video and feedback gain have been taken (these values should be regarded as examples). For special applications actual values have to be taken instead. White point must be aligned at maximum luminance (e.g. at 102.8 cd/m2) with maximum contrast and nominal brightness. It is recommended to use only a small white square for white point alignment, to prevent variations of the voltage at grid G1 (Vg1) and grid G2 (Vg2) and to prevent unwanted activation of the automatic beam limiter (ABL). For practical reasons, alignment of the R, G, B reference black levels must be done with a small amount of drive for obtaining a luminance level of approximately 2.4 cd/m2. This drive can be simulated by setting the brightness to a certain value. Assuming 102.8 cd/m2 luminance with full white video (100% drive) and a cathode characteristic with gamma = 2.25, the drive for black level adjustment can be shown as: 2.4 -------------------------- x 100 = 18.8% drive 1/2.25 102.8 which corresponds to a brightness setting of B8H. After black level adjustment for L = 2.4 cd/m2, the cathode voltages are fixed and the cut-off voltages are set with equal gain condition in all channels. During white point adjustment the gains will be changed. In the factory procedure for single pass adjustment, the luminance level for black level alignment (2.4 cd/m2) is kept constant while adjusting the gain settings. To achieve this, the black level references are compensated by software and an alignment computer (this compensation is for factory alignment only and is not needed for any user change of R, G, B gain). 44
High electric field strength is present between the gun electrodes of picture tubes. In case of a flashover large transient currents and voltages may damage electronic components. It is therefore important to provide protective circuits with spark gaps, series resistors and protection diodes. Be aware that not only electronic components that are directly connected to the tube socket are endangered if interconnection lines on the application board are unfavourably routed. 12.4 12.4.1 Application hints ALIGNMENT RECOMMENDATIONS USING BRIGHTNESS
CONTROL WITH GREY SCALE TRACKING
12.4.1.1
Introduction (philosophy of TDA4887PS)
With the TDA4887PS the user may change contrast, brightness and even colour temperature (R, G, B gains) or any combination at will. The `x,y' colour point will remain stable for the full grey scale. This feature is achieved in the following way: A change of brightness will cause a change of black level which is proportional to the actual gain setting Conversely, a change of gain setting will cause a change of black level that is proportional to the deviation of brightness from its nominal setting. To benefit fully from this colour tracking feature, the reference black levels of the video amplifiers must match exactly to the cut-off points of the cathodes. Re-adjustments of black level settings by the end user should be avoided, because this will upset the tracking feature. 2001 Oct 19
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
Calculation of compensation (see Fig.22): 1. Gain adjustment is in 255 steps from 20 to 100% which equates to 4.6 V per step at maximum contrast. 0.8 x 4.6 V One step = --------------------------- = 14.4 mV which is equal to 255 187 mV at the cathode with video gain = 13 for the white area. 2. For 18.8% drive (used for black level adjustment) the output changes only 2.7 mV (35 mV at the cathode) per gain step.
TDA4887PS
3. The black level adjustment range (at feedback inputs) is 1.9 V in 255 steps, which is 7.45 mV per step ( black level of 97 mV at the cathode with feedback gain = 113). It follows that the optimum compensation 97 is one step black level for ----- = 2.8 or approximately 35 three steps of gain.
handbook, full pagewidth
0.7 V (nom.)
FIXED MAXIMUM GAIN 4.6/0.7 V
CONTRAST -40 dB (0.5/100%) 255 steps
BRIGHTNESS -10/30% of 4.6 V 255 steps
3 x GAIN 20/100% 255 steps
4.6 V (max.)
VIDEO GAIN
signal amplitude 60 V (max.) CRT
13
PREAMPLIFIER
3 x BLACK REFERENCES range 1.9 V 255 steps
FEEDBACK GAIN 5.75 to 3.95 V
1/13
MHB953
25 V cut-off level variation
Fig.22 Signal amplification and feedback references.
12.4.1.4
Example of automatic factory alignment
2. Vg2 and black levels a) Set brightness to 18.8% drive (B8H, subaddress 01H, control bit BRI=0) b) Apply black video c) Increase Vg2 manually until one colour appears d) Activate the alignment computer e) The computer will continuously adjust the R, G, B black levels to meet the following three conditions: x = 0.131 y = 0.329 the centre of the min/max setting remains at 80H (this will leave some margin for the compensation steps that follow) f) Fine tuning of Vg2 (or Vg1) until Y = 2.4 cd/m2 with the computer still active.
This procedure shows a realization of the alignment description, it depends on disposable equipment. Gamma = 2.25, maximum luminance = 102.8 cd/m2, video gain = 13, feedback gain = 113, white D; see Fig.23. 1. Initialization a) Set grid 2 voltage to minimum b) Set R, G, B gains to the centre values (80H, subaddresses 04H, 05H, 06H) c) Set R, G, B black references to centre values (80H, subaddresses 07H, 08H, 09H) d) Set contrast to maximum (FFH, subaddress 02H).
2001 Oct 19
45
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
3. R, G, B gains (white point) a) Set brightness at nominal (40H) b) Apply full video white area (700 mV) c) Activate the computer d) The computer will adjust the R, G, B gains to meet the following three conditions: x = 0.313 y = 0.329 Y = 102.8 cd/m2 For each 3 (2.8) gain increments, the computer will decrement the black references by one step.
TDA4887PS
The effect on cathode voltages is demonstrated in Fig.23. After step 2 the voltages at 18.8% drive are correct but not those at 100% drive (white) and 0% (black). After step 3 the voltages at 18.8% drive have not changed but white as well as black voltages are correct now. Any brightness setting (-10 to +30%) relates to the individual maximum video amplitude (black-to-white). This alignment procedure is adaptable to DC-coupled as well as AC-coupled cathodes.
handbook, full pagewidth
80
cut-off voltage range from black level references (13 x 5.75 to 13 x 3.95)
cathode voltage (V) 70 black 60 18.8% 50
40
30
white
20
step 1: Black level references and gain set to 80H.
10
step 2: Black level references adjusted with 18.8% drive and gain set to 80H.
step 3: Gain adjustment at 100% white with automatic black level reference correction. Cathode voltages for 18.8% drive left unchanged.
0
MHB954
Fig.23 Automatic factory alignment.
2001 Oct 19
46
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
12.4.2 BLACK LEVEL RESTORATION
TDA4887PS
The upper circuit has much less temperature dependence on clamp voltage and, in the event of an I2C-bus Power-on reset in TDA4887PS, all clamp voltages go to black. For correct clamping, a well-defined top level of Vsig is necessary (pedestal black level has to be the most positive voltage). When using internal brightness control, pedestal blanking (subaddress 0BH) has to be larger than minimum possible brightness setting (10% of maximum signal swing if the complete range is used). With 40 V maximum signal swing and 15% pedestal blanking, the clamping voltage Vcl has to be 6 V higher than the extended cut-off voltage. Without using internal brightness control, at least 5% pedestal blanking is recommended.
Figure 24 shows two simple circuits for black level restoration for applications with AC-coupled cathodes. The output signal of the post amplifier is coupled via a 1 F capacitor and a 68 resistor to the cathode. The cathode voltage is clamped (peak responding) to the DC voltage Vcl = Vb + VBE via diode D1. The voltage Vb is derived from the bus controlled reference voltage Vref (pin FB/R(n) of TDA4887PS) by resistor network R1 to R2. R1 + R2 V b = V a x -------------------- for the upper circuit. R1 R2 V b = V p1 - ( V a1 - V be ) x ------ for the lower circuit. R1
handbook, full pagewidth
Vp1 VIDEO BOOSTER amplification 13 Vsig
90 V BAV21 Rc 22 k 1 M Vcl D1 68 BAW62 Vb R2 150 k Va R1 12 k amplification 13.5 1 F cathode
1 F
Vp2
8V
TDA4887PS
Vref
2x BC546
Re 560
Vp1 VIDEO BOOSTER amplification 13 Vsig
100 V BAV21 R2 150 k 1 M Vcl D1 68 BAW62 Vb amplification -15 1 F cathode
1 F
TDA4887PS
Vref
BC546
Va1 R1 10 k
MHB955
Fig.24 Black level restoration circuits.
2001 Oct 19
47
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
12.4.3 AVOIDING NEGATIVE INPUT VOLTAGES AT BLANKING
AND CLAMPING INPUT PINS
TDA4887PS
combination with an external resistor protects the pins from negative voltages (see Fig.25). At pin voltages near to ground level, the voltage difference between the internal reference voltage Vref and the base voltage of TR1, which is 2VBE higher than the pin voltage, generates a current through R1 which is amplified to the output by transistor TR1. The voltage drop at the external resistor Rext stabilizes voltage Vpin near ground. The recommended value for Rext is 1 k.
Negative voltages on any input pin causes ESD protection diodes and other internal junctions will become open-circuit resulting in substrate current injection. Substrate currents can generate parasitic effects that are not completely predictable. Signal inputs (pins 6 and 10) are neighbouring clamping inputs (pins 5 and 11) and can therefore suffer from larger leakage currents during negative clamping pulse glitches. An internal circuit in
handbook, full pagewidth
Vref = 2VBE R1 6 k VP 8V TR1 TDA4887PS TR3 ground clamping pulse Vi Rext Vpin junctions from pin to substrate
MHB956
TR2
Fig.25 Protection circuit at pins CLI and HFB.
2001 Oct 19
48
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 13 INTERNAL CIRCUITRY 2001 Oct 19 49 3 OSD2; OSD input channel 2 open-circuit base
5V VP 3 1 k VP 50 A 0V
MHA653
Philips Semiconductors
160 MHz bus-controlled monitor video preamplifier
PIN 1
SYMBOL AND DESCRIPTION FBL; fast blanking input for OSD insertion
CHARACTERISTIC open-circuit base
WAVEFORM
5V VP 0V
MHA653
EQUIVALENT CIRCUIT
50 A signal blanking 1 1 k 50 A OSD1 blanking 50 A OSD2 blanking 50 A OSD3 blanking
MHA928
2
OSD1; OSD input channel 1
open-circuit base
5V VP 2 1 k
VP 50 A signal blanking
0V
MHA653
disable OSD
1 k FBL
MHB197
signal blanking
disable OSD
1 k FBL
MHB198
TDA4887PS
Product specification
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5
Philips Semiconductors
PIN 4
SYMBOL AND DESCRIPTION OSD3; OSD input channel 3
160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC open-circuit base
WAVEFORM
5V VP 4
EQUIVALENT CIRCUIT
VP 50 A signal blanking 1 k disable OSD
0V
MHA653
1 k FBL
MHB199
5
CLI; vertical blanking input, input clamping input
VCLI > 0.2 V: open-circuit base VCLI 0.2 V: source current rising with decreasing voltage
MHA651
5V 2.5 V 0V
2VBE 6 k
VP 10 k
26 A
3 V + VBE VP
1 k 10 k power on/down
MHA619
TDA4887PS
Product specification
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160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC outside clamping pulse: open-circuit base with base current compensation II1 during clamping: -420 to +420 A
WAVEFORM
4.7 V black shoulder video signal sync 4V 3.7 V 6
dbook, halfpage
EQUIVALENT CIRCUIT
MIRROR 1:1
VP
VP
input clamping (pin 5)
MHA652
700 1.8 V + VBE signal 420 A 0 A
MHB926
240 A
220 A
7
VP; supply voltage
IP = 25 mA (typical)
7
MHA621
TDA4887PS
Product specification
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4.7 V black shoulder video signal sync 4V 3.7 V 10
book, halfpage
Philips Semiconductors
PIN 8
SYMBOL AND DESCRIPTION VI2; signal input channel 2
160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC outside clamping pulse: open-circuit base with base current compensation II2 during clamping: -420 to +420 A
WAVEFORM
4.7 V black shoulder video signal sync 4V 3.7 V 8
book, halfpage
EQUIVALENT CIRCUIT
MIRROR 1:1
VP
VP
input clamping (pin 5)
MHA652
700 1.8 V + VBE signal 420 A 0 A
MHB927
240 A
220 A
9
GND; ground
9
MHA623
MIRROR 1:1
VP
VP
input clamping (pin 5)
MHA652
700 1.8 V + VBE signal 420 A 0 A
MHB923
TDA4887PS
Product specification
240 A
220 A
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160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC VHFB > 0.2 V: open-circuit base VHFB 0.2 V: source current rising with decreasing voltage
WAVEFORM
5V 0V
MHA649
EQUIVALENT CIRCUIT
2VBE 6 k VP 10 k 27 A clamping 27 A blanking 12 k
VP
3 V + VBE 1 k
1.7 V 10 k
11
power on/down
MHA625
12
SDA; I2C-bus serial data input/output
no acknowledge: open-circuit base during acknowledge: ISDA > 3 mA
5V 0V
MHA647
halfpage
6 A
70 A
19 A
10 k 12
2.46 V + VBE
acknowledge
MHB924
open-circuit base
5V 0V
MHA648
alfpage
19 A 1 k
TDA4887PS
13 2.46 V + VBE
MHB925
Product specification
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brightness 10 A
Philips Semiconductors
PIN 14
SYMBOL AND DESCRIPTION GNDX; ground signal channels 1, 2 and 3 VP3; supply voltage channel 3
160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC
WAVEFORM
EQUIVALENT CIRCUIT
14
MHB205
15
IP3 = 20 mA (typical)
15
MHB206
16
reference black level VO3; signal output channel 3 voltage 0.1 to 2.8 V
brightness
MHA655
VP 2 k
reference black level during output clamping 16
MHA656
VP 1 k 75 1.5 k 1 k 3.5 pF
60 fF 8 k
control bit PEDST = 0
pedestal black level during output clamping
MHB957
control bit PEDST = 1
TDA4887PS
Product specification
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1 k 5.75 to 2.55 V
Philips Semiconductors
PIN 17
SYMBOL AND DESCRIPTION
160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC
age
WAVEFORM
feedback reference 5.75 to 2.55 V VP PEDST = 0 17 PEDST = 1
EQUIVALENT CIRCUIT
FB/R3; feedback open-circuit base input/ reference voltage output channel 3
27 I 100
2I
5.75 to 2.55 V
MHB931
control bit FPOL = 0 IFB/R3: -200 to +200 A VFB/R3: 5.75 to 2.55 V control bit FPOL = 1
1 k 1.7 k I
10 A
10 A
15 k Vs1 15 k Vs2
MHB928
DC coupling (control bit FPOL = 0): Vs1 = 0 V; Vs2 = 1 V; I = 0 AC coupling (control bit FPOL = 1): Vs1 = 1 V; Vs2 = 0 V; I = 7.5 A
18
VP2; supply voltage channel 2
I18 = 20 mA (typical)
18
TDA4887PS
Product specification
MHB218
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160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC
WAVEFORM
MHA655
EQUIVALENT CIRCUIT
VO2; signal reference black level output channel 2 voltage 0.1 to 2.8 V
brightness
VP 2 k
reference black level during output clamping 19
MHA656
VP 1 k 75 1.5 k 1 k 3.5 pF 10 A
60 fF 8 k
control bit PEDST = 0 pedestal black level voltage 0.1 to 2.8 V
brightness
pedestal black level during output clamping
MHB958
TDA4887PS
Product specification
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1 k 5.75 to 2.55 V
Philips Semiconductors
PIN 20
SYMBOL AND DESCRIPTION
160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC
age
WAVEFORM
feedback reference 5.75 to 2.55 V VP PEDST = 0 20 PEDST = 1
EQUIVALENT CIRCUIT
FB/R2; feedback open-circuit base input/reference voltage output channel 2
27 I 100
2I
5.75 to 2.55 V
MHB931
control bit FPOL = 0 IFB/R2: -200 to +200 A VFB/R2: 5.75 to 2.55 V control bit FPOL = 1
1 k 1.7 k I
10 A
10 A
15 k Vs1 15 k Vs2
MHB929
DC coupling (control bit FPOL = 0): Vs1 = 0; Vs2 = 1 V; I = 0 AC coupling (control bit FPOL = 1): Vs1 = 1 V; Vs2 = 0; I = 7.5 A
21
VP1; supply voltage channel 1
IP1 = 20 mA (typical)
21
TDA4887PS
Product specification
MHB211
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160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC
WAVEFORM
MHA655
EQUIVALENT CIRCUIT
VO1; signal reference black level output channel 1 voltage 0.1 to 2.8 V
brightness
VP 2 k
reference black level during output clamping 22
MHA656
VP 1 k 75 1.5 k 1 k 3.5 pF 10 A
60 fF 8 k
control bit PEDST = 0 pedestal black level voltage 0.1 to 2.8 V
brightness
pedestal black level during output clamping
MHB959
TDA4887PS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Oct 19 59
1 k 5.75 to 2.55 V
Philips Semiconductors
PIN 23
SYMBOL AND DESCRIPTION
160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC
age
WAVEFORM
feedback reference 5.75 to 2.55 V VP PEDST = 0 23 PEDST = 1
EQUIVALENT CIRCUIT
FB/R1; feedback open-circuit base input/reference voltage output channel 1
27 I 100
2I
5.75 to 2.55 V
MHB931
control bit FPOL = 0 IFB/R1: -200 to +200 A VFB/R1: 5.75 to 2.55 V control bit FPOL = 1
1 k 1.7 k I
10 A
10 A
15 k Vs1 15 k Vs2
MHB930
DC coupling (control bit FPOL = 0): Vs1 = 0; Vs2 = 1 V; I = 0 AC coupling (control bit FPOL = 1): Vs1 = 1 V; Vs2 = 0; I = 7.5 A
TDA4887PS
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Oct 19 60 Philips Semiconductors PIN 24 SYMBOL AND DESCRIPTION LIM; subcontrast adjustment, contrast modulation, beam current limiting input
160 MHz bus-controlled monitor video preamplifier
CHARACTERISTIC open-circuit voltage VLIM = 5 V VLIM < 4.4 V: open-circuit base
WAVEFORM
VP
EQUIVALENT CIRCUIT
21 A 1 k 5.0 V 10 k
24
MHB214
TDA4887PS
Product specification
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
14 PACKAGE OUTLINE SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
TDA4887PS
SOT234-1
D seating plane
ME
A2
A
L
A1 c Z e b 24 13 b1 wM (e 1) MH
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 22.3 21.4 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT234-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
2001 Oct 19
61
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
15 SOLDERING 15.1 Introduction to soldering through-hole mount packages
TDA4887PS
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 15.3 Manual soldering
This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 15.2 Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. 15.4
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING WAVE suitable(1)
DBS, DIP, HDIP, SDIP, SIL Note
suitable
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
2001 Oct 19
62
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
16 DATA SHEET STATUS DATA SHEET STATUS(1) Objective specification PRODUCT STATUS(2) Development DEFINITIONS
TDA4887PS
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary specification
Qualification
Product specification
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2001 Oct 19
63
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
19 PURCHASE OF PHILIPS I2C COMPONENTS
TDA4887PS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2001 Oct 19
64
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
NOTES
TDA4887PS
2001 Oct 19
65
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
NOTES
TDA4887PS
2001 Oct 19
66
Philips Semiconductors
Product specification
160 MHz bus-controlled monitor video preamplifier
NOTES
TDA4887PS
2001 Oct 19
67
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp68
Date of release: 2001
Oct 19
Document order number:
9397 750 08393

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